To face the growing complexity of System-on-Chips (SoCs) and their tight time-to-market constraints, Virtual Prototyping (VP) tools based on SystemC/TLM2.0 must get faster while maintaining accuracy. However, the ASI SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present SCale 2.0, a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented simulation speeds. By coupling a parallel SystemC kernel with shared resources access monitoring and process-level rollback, we can preserve SystemC atomic thread evaluation while leveraging the available host cores. We also generate process interaction traces that can be used to replay any simulation deterministically for debug purpose. Evaluation on baremetal applications shows × 15 speedup compared to the ASI SystemC kernel using 33 host cores reaching speeds above 2300 Million simulated Instructions Per Second (MIPS). Challenges related to parallel simulation of full software stack with modern operating systems are also addressed with speedup reaching × 13 during recording run and × 24 during the replay run.

要面对日益增长的片上系统（SoC）的复杂性及其严格的上市时间限制，基于SystemC / TLM2.0的虚拟原型（VP）工具必须在保持准确性的前提下变得更快。但是，ASI SystemC参考实现仍然是顺序的，无法利用现代工作站的多个核心。在本文中，我们介绍了SCale 2.0，这是并行和符合标准的SystemC内核的新实现，可达到空前的仿真速度。通过将并行SystemC内核与共享资源访问监视和进程级回滚相结合，我们可以在利用可用主机内核的同时保留SystemC原子线程评估。我们还生成过程交互跟踪，这些跟踪可用于确定性地重播任何模拟以进行调试。与使用33个主机内核的ASI SystemC内核相比，对裸机应用程序的评估显示出×15的加速，达到每秒2300百万模拟指令（MIPS）以上的速度。通过在录制运行期间达到×13，在回放运行期间达到×24的速度，还解决了与使用现代操作系统对完整软件堆栈进行并行仿真有关的挑战。