DC-offset in the input of the phase-locked loop (PLL) is an emerging problem that causes oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude. The DC-offset rejection in grid synchronization is a difficult task due to its low-frequency nature. This paper proposes a method to remove the DC-offset in the single-phase grid synchronization utilizing delay signal cancellation (DSC) and a variable-length time delay (VLTD) based PLL. The small-signal model, stability analysis, and controller gains selection are discussed. The proposed PLL is compared with other single-phase PLLs in terms of the phase settling time, the phase percent maximum overshoot, and the peak of the estimated frequency, to show its advantages.

锁相环（PLL）输入中的DC偏移是一个新出现的问题，会导致估计的基本电网相位，频率和电压幅度发生振荡。电网同步中的直流偏移抑制由于其低频特性而成为一项艰巨的任务。本文提出了一种利用基于延迟信号消除（DSC）和基于可变长度时间延迟（VLTD）的PLL消除单相电网同步中的直流偏移的方法。讨论了小信号模型，稳定性分析和控制器增益选择。拟议的PLL在相位建立时间，相位百分比最大过冲和估计频率的峰值方面与其他单相PLL进行了比较，以显示其优势。