This paper proposes a high-speed deterministic digital technique to calibrate the errors due to capacitance mismatch and finite op-amp gain. Unlike other calibration techniques, this technique requires neither forcing the inputs of the intermediate stages being calibrated to exact voltages, nor reducing the gains of each stage to avoid saturation of output digital codes. A 1.5 bits/stage, 10 stages, 9 bits pipeline ADC with the three most significant stages calibrated is demonstrated in this paper. For a 10% mismatch in capacitances in the 3 MSB stages of the pipelined ADC, the calibration technique improved SNDR by more than 20 dB and SFDR by around 27 dB. The technique can also be slightly modified to calibrate algorithmic ADCs. For a 7% mismatch in capacitances of the algorithmic ADC, the proposed calibration technique improved SNDR by 18 dB and SFDR by around 28 dB.

本文提出了一种高速确定性数字技术，以校准由于电容失配和有限运算放大器增益而引起的误差。与其他校准技术不同，该技术既不需要将被校准的中间级的输入强制为精确的电压，也不需要降低每个级的增益来避免输出数字代码的饱和。本文演示了一个1.5位/级，10级，9位流水线ADC，并校准了三个最高有效级。对于流水线ADC的3个MSB级中的电容失配10％，该校准技术将SNDR提高了20 dB以上，将SFDR提高了约27 dB。该技术也可以稍作修改以校准算法ADC。对于算法ADC的7％的电容失配，