Bonded interfaces in power converters add thermal resistances to heat dissipation. Under cyclic power, temperature, or chemical loading, these interfaces degrade, raising the thermal resistances. Reliability of the thermal interfaces is especially problematic when the bonded area is large because the larger the area the more likely it is to have preexisting defects from processing. To help qualifying the development of a bonding process and quantifying the interface reliability, it would be desirable to have a simple, reliable, and nondestructive measurement technique to obtain a 2-D map of the interface thermal resistance across a large bonded area. Based on the transient thermal method of JEDEC standard 51-14, in this article, we develop a measurement technique that involves moving a thermal probe discretely across a large-area bonded substrate and acquiring the thermal interface resistance under the probe at each location. The probe is made by custom-packaging an insulated-gate bipolar transistor (IGBT) power device. An analytical thermal model is developed to gain insights into the effects of probe materials and structural parameters on the sensitivity of the measurement technique. To obtain a 2-D thermal resistance map of a bonded substrate, the probe is thermally coupled to the substrate at one location through a thermal pad or grease; the device is powered up to a steady-state junction temperature; the power is cutoff; and then the junction temperature during cool-down is recorded. The recorded temperature data are analyzed to derive a thermal structure function of the multilayer material stack. The process is repeated at other locations until a 2-D map of the interface thermal resistance across the entire substrate is completed. This technique is demonstrated on copper-copper bonded samples using either a thermal grease or sintered silver. The resolution of the 2-D mapping technique is evaluated by a copper-grease-copper stack with defects implanted at the bond line.

中文翻译：

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通过瞬态热测量绘制界面热阻二维图


功率转换器中的粘合接口增加了散热的热阻。在循环功率、温度或化学负载下，这些界面会退化，从而提高热阻。当粘合面积较大时，热界面的可靠性尤其成问题，因为面积越大，越有可能因加工而存在预先存在的缺陷。为了帮助鉴定键合工艺的开发并量化界面可靠性，需要一种简单、可靠且无损的测量技术来获得大键合区域的界面热阻的二维图。基于 JEDEC 标准 51-14 的瞬态热方法，在本文中，我们开发了一种测量技术，该技术涉及在大面积粘合基板上离散地移动热探针，并获取探针下方每个位置的热界面电阻。该探头是通过定制封装绝缘栅双极晶体管 (IGBT) 功率器件制成的。开发了分析热模型，以深入了解探针材料和结构参数对测量技术灵敏度的影响。为了获得粘合基板的二维热阻图，探针通过导热垫或油脂在一个位置热耦合到基板；该器件加电至稳态结温；电源被切断；然后记录冷却期间的结温。分析记录的温度数据以导出多层材料堆叠的热结构函数。在其他位置重复该过程，直到完成整个基板的界面热阻的二维图。 该技术在使用导热油脂或烧结银的铜-铜粘合样品上进行了演示。二维测绘技术的分辨率通过在接合线处植入缺陷的铜-油脂-铜叠层来评估。