Multiplication is one of the most extensively used arithmetic operations in a wide range of applications. In order to provide resourceefficient and high-performance multipliers, previous works have proposed different designs of accurate and approximate multipliers—mainly for ASIC-based systems. However, the architectural differences between ASICs and FPGA-based systems limit the effectiveness of these multipliers for FPGA-based systems. Moreover, most of these multiplier designs are valid only for unsigned numbers. To bridge this gap, we propose a novel implementation technique for designing resourceefficient and low-power accurate and approximate signed multipliers which are optimized for FPGA-based systems. Compared to Vivado’s area-optimized multiplier IPs, the designs obtained using our proposed technique occupy 47% to 63% less area (Lookup Tables). To accelerate further research in this direction and reproduce the presented results, the RTL and behavioral models of our proposed methodology are available as an open-source library at https:// cfaed.tu-dresden.de/ pd-downloads.

中文翻译：

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面积优化的精确和近似软核有符号乘法器架构

乘法是广泛应用中使用最广泛的算术运算之一。为了提供资源高效和高性能的乘法器，以前的工作提出了精确和近似乘法器的不同设计——主要是针对基于 ASIC 的系统。然而，ASIC 和基于 FPGA 的系统之间的架构差异限制了这些乘法器对于基于 FPGA 的系统的有效性。此外，大多数这些乘法器设计仅对无符号数有效。为了弥补这一差距，我们提出了一种新颖的实现技术，用于设计资源高效且低功耗的精确和近似有符号乘法器，这些乘法器针对基于 FPGA 的系统进行了优化。与 Vivado 的面积优化乘法器 IP 相比，使用我们提出的技术获得的设计占用的面积减少了 47% 到 63%（查找表）。为了加快在这个方向上的进一步研究并重现所呈现的结果，我们提出的方法的 RTL 和行为模型可作为开源库在 https://cfaed.tu-dresden.de/pd-downloads 上获得。