Transistor threshold voltage (V_t) scaling causes higher power consumption by increasing the subthreshold leakage and short-circuit currents in CMOS circuits. Leakage currents are significant contributors to the overall power consumption of digital systems-on-chip as threshold voltage, channel length, and gate oxide thickness are reduced with CMOS technology scaling. A new dual-pullup/dual-pulldown (DPU/DPD) repeater is proposed in this paper for higher energy efficiency in low-voltage and low-frequency applications. The standby mode leakage power consumption is reduced by 59.11% with the proposed clock tree as compared to the conventional 3 level H-tree operating with a power supply voltage of 1.0V in a 45 nm CMOS technology. The short-circuit currents are suppressed by selectively employing high-V_t transistors in the repeaters. The clock network with the proposed buffer lowers the active mode energy consumption by up to 24.91% as compared to a conventional clock tree under equal silicon area constraint. Post layout results reveal that the statistical spread of clock skew in the DPU/DPD H-tree is also 20.60% lower than the conventional H-tree network.

晶体管阈值电压（V _t）缩放会增加CMOS电路中的亚阈值泄漏和短路电流，从而导致更高的功耗。漏电流是芯片数字系统总体功耗的重要因素，因为随着CMOS技术的发展，阈值电压，沟道长度和栅氧化层厚度都得以减小。本文提出了一种新型的双上拉/双上拉（DPU / DPD）中继器，以提高低压和低频应用中的能效。与在45 nm CMOS技术中以1.0V的电源电压工作的常规3级H树相比，采用建议的时钟树可将待机模式泄漏功耗降低59.11％。通过有选择地采用高V电压来抑制短路电流中继器中的_t个晶体管。与具有相同硅面积约束的常规时钟树相比，具有建议的缓冲器的时钟网络可将主动模式能耗降低多达24.91％。布局后的结果表明，DPU / DPD H树中时钟偏斜的统计分布也比常规H树网络低20.60％。