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A data‐independent 9T SRAM cell with enhanced ION/IOFF ratio and RBL voltage swing in near threshold and sub‐threshold region
International Journal of Circuit Theory and Applications ( IF 1.8 ) Pub Date : 2021-02-03 , DOI: 10.1002/cta.2951 Monica Gupta 1, 2 , Kirti Gupta 2 , Neeta Pandey 1
International Journal of Circuit Theory and Applications ( IF 1.8 ) Pub Date : 2021-02-03 , DOI: 10.1002/cta.2951 Monica Gupta 1, 2 , Kirti Gupta 2 , Neeta Pandey 1
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The conventional 8T SRAM cell with isolated read port is suggested as an alternative to overcome the read‐write conflicts associated with 6T SRAM cell. However, in near threshold and sub‐threshold regions, 8T cell performance is limited by reduced ION/IOFF ratio, deteriorated RBL voltage swing, data dependency, and higher read failures, although the existing SRAM cells address some of these issues but still suffer from degraded performance due to the trade‐off between leakage and read currents. In this paper, a 9T SRAM cell with novel read port is proposed that aims for low and data‐independent leakages, high ION/IOFF ratio, and large RBL voltage swing in near threshold and sub‐threshold regions. The performance of the proposed cell is compared with 7T, 8T, 9T, and 10T cells at 32 nm technology node by simulating a column of 128 cells to demonstrate its versatility over others. The proposed cell shows enhanced ION/IOFF ratio (71.2X), large RBL voltage swing and data‐independent leakages at VDD = 0.3 V in comparison to the conventional 8T SRAM cell. The results at different PVT corners are also captured to validate the impeccable performance of the proposed cell irrespective of operating conditions.
中文翻译：
一个独立于数据的9T SRAM单元，在接近阈值和亚阈值区域时具有增强的ION / IOFF比和RBL电压摆幅
建议使用具有隔离读取端口的常规8T SRAM单元来替代与6T SRAM单元相关的读写冲突。但是，在接近阈值和亚阈值区域中，尽管现有的SRAM单元解决了其中的一些问题，但降低的I ON / I OFF比率，恶化的RBL电压摆幅，数据依赖性以及更高的读取故障限制了8T单元的性能。由于泄漏电流和读取电流之间的折衷，使性能下降。本文提出了一种具有新型读取端口的9T SRAM单元，该单元旨在实现低泄漏和与数据无关的泄漏，高I ON / I OFF比率和较大的RBL电压摆幅在阈值和亚阈值附近。通过模拟128个单元的列以证明其在其他方面的多功能性，在32 nm技术节点上将拟议的单元的性能与7T，8T，9T和10T单元进行了比较。与传统的8T SRAM单元相比，拟议的单元在I DD的I ON / I OFF比率（71.2倍），较大的RBL电压摆幅和V DD = 0.3 V时与数据无关的泄漏方面表现出优势。还捕获了不同PVT拐角处的结果，以验证所提出电池的无可挑剔的性能，而不管其工作条件如何。
更新日期：2021-04-08
中文翻译：
一个独立于数据的9T SRAM单元，在接近阈值和亚阈值区域时具有增强的ION / IOFF比和RBL电压摆幅
建议使用具有隔离读取端口的常规8T SRAM单元来替代与6T SRAM单元相关的读写冲突。但是，在接近阈值和亚阈值区域中，尽管现有的SRAM单元解决了其中的一些问题，但降低的I ON / I OFF比率，恶化的RBL电压摆幅，数据依赖性以及更高的读取故障限制了8T单元的性能。由于泄漏电流和读取电流之间的折衷，使性能下降。本文提出了一种具有新型读取端口的9T SRAM单元，该单元旨在实现低泄漏和与数据无关的泄漏，高I ON / I OFF比率和较大的RBL电压摆幅在阈值和亚阈值附近。通过模拟128个单元的列以证明其在其他方面的多功能性，在32 nm技术节点上将拟议的单元的性能与7T，8T，9T和10T单元进行了比较。与传统的8T SRAM单元相比，拟议的单元在I DD的I ON / I OFF比率（71.2倍），较大的RBL电压摆幅和V DD = 0.3 V时与数据无关的泄漏方面表现出优势。还捕获了不同PVT拐角处的结果，以验证所提出电池的无可挑剔的性能，而不管其工作条件如何。
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