Ever since the reliability issues caused by I/O (input/output) compatibility among chips fabricated using different processes were raised during mid-2000, on-silicon mixed-voltage I/O buffer with wide voltage tolerance has been considered a better solution than using signal level converters to shrink PCB size, number of discretes, and power consumption. However, various external voltages on I/O pad result in body effect, leakage, hot-carrier degradation, and gate-oxide overstress in stacked transistors of mixed-voltage I/O. What even worse is that slew rate (SR) was also found deteriorated by PVT (Process, Voltage, Temperature) variations. A complete mixed-voltage I/O buffer design flow using nano-scale CMOS processes will be introduced in this tutorial based on previously developed buffers. Besides circuit design methodology, the reliability design consideration for the buffers, including ESD, PVT detection, and slew rate auto-adjustment will be discussed as well.

中文翻译：

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教程：对PVTL变化具有高度可靠性的高速纳米级CMOS混合电压数字I / O缓冲器的设计

自从2000年中期提出使用不同工艺制造的芯片之间的I / O（输入/输出）兼容性所引起的可靠性问题以来，具有宽电压容限的片上混合电压I / O缓冲器被认为是比之更好的解决方案。使用信号电平转换器来缩小PCB尺寸，离散数量和功耗。但是，在混合电压I / O的堆叠晶体管中，I / O焊盘上的各种外部电压会导致体效应，泄漏，热载流子退化和栅极氧化物过应力。更糟糕的是，还发现压摆率（SR）也因PVT（工艺，电压，温度）变化而恶化。本教程将基于以前开发的缓冲器，介绍使用纳米级CMOS工艺的完整混合电压I / O缓冲器设计流程。除了电路设计方法之外，