As we target implementations of very high-end () specifications and look towards the future, it becomes apparent that the stringent execution deadlines in physical layer (PHY) procedures are hard to satisfy using traditional algorithms optimised for high throughput. Hence, if the designer adheres to the same throughput efficient algorithm and simply scales up the hardware (HW), the device effectively becomes overprovisioned, costing more than it would if the designer opted for a latency efficient algorithm. However, latency efficient algorithms cost more operations per transmitted data item, and therefore consume more power compared to throughput efficient algorithms. Consequently, if the designer opts for latency efficient algorithms, the implementation would be power inefficient for all but the latency-critical use cases. We identify the use-cases where these problems occur in the channel estimation (CE) PHY procedure and propose a software (SW) implementation that can dynamically switch between latency and throughput efficient algorithms and thereby avoid both unnecessary HW overprovisioning and excess power consumption. In this article we demonstrate this with an example implementation of CE for the high-end and quantify the benefits of this approach.

中文翻译：

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矢量数字信号处理器上高级5G / 6G用例的信道估计

当我们以非常高端（）规范的实现为目标并展望未来时，很明显，严格的执行截止日期是 物理层（PHY）程序使用针对高吞吐量进行了优化的传统算法很难满足。因此，如果设计人员坚持使用相同的吞吐效率算法，并简单地扩大规模，硬件（HW），该设备实际上被过度配置，其成本比设计人员选择延迟有效算法的成本高。但是，延迟高效的算法每个传输的数据项花费更多的操作，因此与吞吐量高效的算法相比，消耗更多的功率。因此，如果设计人员选择了延迟有效的算法，那么对于所有对延迟至关重要的用例，实施方式在功效上都是低效的。我们确定了在这些情况下发生这些问题的用例信道估计 （CE）PHY程序并提出 软件（SW）实现，可以在等待时间和吞吐量高效的算法之间动态切换，从而避免不必要的硬件过量配置和过多的功耗。在本文中，我们以高端CE的示例实现为例进行了演示，并量化了此方法的好处。