In 5G New Radio (NR), low-density parity-check (LDPC) codes are included as the error correction codes (ECC) for the data channel. While LDPC codes enable a low, near Shannon capacity, bit error rate (BER), they also become a computational bottleneck in the physical layer processing. Moreover, 5G LDPC has new challenges not seen in previous LDPC implementations, such as Wi-Fi. The LDPC specification in 5G includes many reconfigurations to support a variety of rates, block sizes, and use cases. 5G also creates targets for supporting high-throughput and low-latency applications. For this new, flexible standard, traditional hardware-based solutions in FGPA and ASIC may struggle to support all cases and may be cost-prohibitive at scale. Software solutions can trivially support all possible reconfigurations but struggle with performance. This article demonstrates the high-throughput and low-latency capabilities of graphics processing units (GPUs) for LDPC decoding as an alternative to FPGA and ASIC decoders, effectively providing the high performance needed while maintaining the benefits of a software-based solution. In particular, we highlight how by varying the parallelization strategy for mapping GPU kernels to blocks, we can use the many GPU cores to compute one codeword quickly to target low-latency, or we can use the cores to work on many codewords simultaneously to target high throughput applications. This flexibility is particularly useful for virtualized radio access networks (vRAN), a next-generation technology that is expected to become more prominent in the coming years. In vRAN, the hardware computational resources will become decoupled from the specific computational functions in the RAN through virtualization, allowing for benefits such as load-balancing, improved scalability, and reduced costs. To highlight and investigate how the GPU can accelerate tasks such as LDPC decoding when containerizing vRAN functionality, we integrate our decoder into the Open Air Interface (OAI) NR software stack. With our GPU-based decoder, we measure a best case-latency of $87~\mu \text{s}$ and a best-case throughput of nearly 4 Gbps using the Titan RTX GPU.

中文翻译：

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基于GPU的LDPC解码，适用于5G及以上

在5G新无线电（NR）中，包括低密度奇偶校验（LDPC）码作为数据通道的纠错码（ECC）。尽管LDPC码实现了低的接近Shannon容量的误码率（BER），但它们也成为物理层处理中的计算瓶颈。此外，5G LDPC具有新的挑战，例如Wi-Fi等以前的LDPC实现中所没有的。5G中的LDPC规范包括许多重新配置，以支持各种速率，块大小和用例。5G还为支持高吞吐量和低延迟应用程序创建了目标。对于这种新的，灵活的标准，FGPA和ASIC中基于硬件的传统解决方案可能难以支持所有情况，并且可能在成本上过于昂贵。软件解决方案可以轻松地支持所有可能的重新配置，但会在性能方面产生困难。本文演示了用于LDPC解码的图形处理单元（GPU）的高吞吐量和低延迟功能，可以替代FPGA和ASIC解码器，在保持基于软件的解决方案的优势的同时，有效地提供所需的高性能。特别是，我们着重强调了如何通过改变将GPU内核映射到块的并行化策略，如何使用多个GPU内核来快速计算一个码字以定位低延迟，或者我们可以使用这些内核同时对多个码字进行处理以实现目标。高通量应用。这种灵活性对于虚拟化无线接入网络（vRAN）尤其有用，vRAN是下一代技术，预计在未来几年将变得越来越重要。在vRAN中，硬件计算资源将通过虚拟化与RAN中的特定计算功能分离，从而带来诸如负载平衡，改进的可伸缩性和降低的成本等优势。为了突出和研究在容器化vRAN功能时GPU如何加速诸如LDPC解码的任务，我们将解码器集成到了露天接口（OAI）NR软件堆栈中。借助基于GPU的解码器，我们可以测量 $ 87〜\ mu \ text {s} $ 使用Titan RTX GPU的最佳情况下吞吐量接近4 Gbps。