PCI Express (PCIe) specification has been doubling the data rate every generation in a backward compatible manner every two to three years. PCIe 6.0 specification will adopt PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach of prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. We propose a new flit-based approach with a lightweight, low-latency FEC coupled with a strong cyclic redundancy check (CRC) and a low-latency link-level retry mechanism to meet the stringent low-latency, high-bandwidth, and high-reliability goals. We also present a new low-power state that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.

中文翻译：

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PCI Express 6.0规范：具有64.0 GT / s PAM-4信令的低延迟，高带宽，高可靠性和具有成本效益的互连

PCI Express（PCIe）规范每两到三年就以向后兼容的方式使每一代的数据速率加倍。PCIe 6.0规范将采用64.0 GT / s的PAM-4信令，以保持与上一代产品相同的信道范围。前向纠错（FEC）机制将抵消PAM-4的高BER。我们提出了一种新的基于flit的方法，该方法具有轻量级，低延迟FEC以及强大的循环冗余校验（CRC）和低延迟链路级重试机制，可以满足严格的低延迟，高带宽和高带宽要求。可靠性目标。我们还提出了一种新的低功耗状态，该状态可确保功耗与带宽使用成比例，而不会影响流量。