Heterogeneous integration allows multiple silicon dies of various technologies and complexity to communicate efficiently using second-level interconnects, interposers, in a single package. The interposer also provides a low-impedance power delivery path between multiple independent power domains. Although the channels are very short and the signal integrity is not a challenge, the huge increase in the transient current of multiple dies and the unique clocking architecture makes the supply noise and timing jitter the limiting factors in designing high-performance multidie systems. In this article, accurate analysis and characterization techniques of noise and jitter in multidie interfaces are presented. Power supply noise and empirically derived jitter models are correlated with measurements and detailed transistor-level circuit simulations, respectively.

中文翻译：

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异构集成系统中高速接口的噪声和抖动特性

异构集成允许使用各种技术和复杂性的多个硅芯片在单个封装中使用第二级互连，中介层进行有效通信。插入器还提供了多个独立电源域之间的低阻抗电源传输路径。尽管通道非常短，信号完整性也不是问题，但多个管芯的瞬态电流的巨大增加以及独特的时钟架构使电源噪声和时序抖动成为设计高性能多管芯系统的限制因素。本文介绍了多管芯接口中噪声和抖动的准确分析和表征技术。电源噪声和根据经验得出的抖动模型与测量结果和详细的晶体管级电路仿真相关，