Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Co-ordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is $189.73\mu W$ which is 63% of the state-of-the-art.

中文翻译：

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RECON：基于资源有效的基于CORDIC的神经元体系结构

由于诸如乘法器和非线性激活函数之类的资源密集型元素，人工神经网络的当代硬件实现面临超额区域需求的负担。本工作通过提出一种资源高效的建议来应对这一挑战坐标旋转数字计算机基于（CORDIC）的神经元体系结构（RECON），可以配置为计算乘累加（MAC）和非线性激活函数（AF）运算。基于CORDIC的体系结构使用线性和三角关系分别实现MAC和AF操作。拟议的设计使用Cadence Virtuoso在所有物理参数下进行的45nm技术进行合成和验证。使用我们的设计实现带符号定点8位MAC，显示面积，延迟和功耗乘积（ALP）减少了60％，并且面积减少了38％，功耗减少了27％，延迟减少了15％最先进的MAC设计。进一步，蒙特卡洛对提出的模型和最新技术都进行了工艺变化和设备不匹配的仿真，以评估动态功率变化中对随机函数的期望。我们设计的动态功率变化表明，最坏情况的平均值为 $ 189.73 \亩W $ 这是最新技术的63％。