Resistive random access memory (ReRAM)-based computing in-memory (CIM) is a promising solution to overcome the von-Neumann bottleneck in conventional computing architectures. We propose a reconfigurable ReRAM architecture using a novel 4T2R bit-cell that supports non-volatile storage and two types of CIM operations: i) ternary content addressable memory (TCAM) and ii) in-memory dot product (IM-DP) for neural networks. The proposed 4T2R cell occupies a smaller area than prior SRAM-based CIM bit-cells. A $128\times128$ ReRAM macro is designed in 40nm CMOS technology. For TCAM operations, it allows a search word-length of 128 bits. For IM-DP operations, it can compute parallel dot products using binary inputs and ternary weights. The simulated search delay for TCAM operation is 0.92 ns at VDD = 0.9 V and the simulated energy efficiency for IM-DP operation is 223.6 TOPS/W at VDD = 0.7 V. Monte-Carlo simulations show a standard deviation of 4.9% in accumulate operation for IM-DP which corresponds to a classification accuracy of 95.7% on the MNIST dataset and 81.7% on the CIFAR-10 dataset.

中文翻译：

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可重配置的4T2R ReRAM计算内存宏，可用于高效边缘应用

基于电阻式随机存取存储器（ReRAM）的内存中计算（CIM）是一种有希望的解决方案，可以克服常规计算体系结构中的von-Neumann瓶颈。我们提出了一种使用新型4T2R位单元的可重配置ReRAM体系结构，该单元支持非易失性存储和两种类型的CIM操作：i）用于神经网络的三元内容可寻址存储器（TCAM）和ii）内存中点积（IM-DP）网络。提出的4T2R单元比以前的基于SRAM的CIM位单元占用的面积小。一种 $ 128 \次128 $ ReRAM宏采用40nm CMOS技术设计。对于TCAM操作，它允许128位的搜索字长。对于IM-DP操作，它可以使用二进制输入和三进制权重来计算并行点积。在VDD = 0.9 V时，TCAM操作的模拟搜索延迟为0.92 ns，在VDD = 0.7 V时，IM-DP操作的模拟能量效率为223.6 TOPS / W。蒙特卡洛仿真显示，累积操作的标准偏差为4.9％ IM-DP的分类准确度对应于MNIST数据集的95.7％和CIFAR-10数据集的81.7％。