The increasing need to run applications for significant data analytics, and the augmented demand of useful tools for big data computing systems has resulted in a cumulative necessity for efficient platforms with high performance and realizable power consumption, for example, chip multiprocessors. Correspondingly, due to the demand for features like shrinkable sizes, and the concurrent need to pack increasing numbers of transistors into a single chip, has led to serious design challenges, consuming a significant of power within high area densities. We present a reconfigurable hybrid cache system for last level cache by the integration of emerging designs, such as STT-RAM with SRAM memories. This approach consists of two phases: off-time and on-time. In off time, training NN is implemented while in the on-time phase, a reconfiguration cache uses a neural network learning approach to predict demanded latency of the running application. Experimental results of a three-dimensional chip with 64 cores show that the suggested design under PARSEC benchmarks provides a speedup in terms of the performance at 25% and improves energy consumption by 78.4% in comparison to non-reconfigurable pure SRAM cache architectures.

中文翻译：

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基于神经网络预测技术的多芯片功耗感知混合缓存

对运行重要数据分析应用程序的需求不断增加，以及对大数据计算系统有用工具的需求不断增加，导致对具有高性能和可实现功耗的高效平台（例如芯片多处理器）的需求不断增加。相应地，由于对尺寸缩小等特性的需求，以及同时需要将越来越多的晶体管封装到单个芯片中，导致严重的设计挑战，在高面积密度内消耗大量功率。我们通过集成新兴设计（例如 STT-RAM 与 SRAM 存储器），为最后一级缓存提供了一种可重构混合缓存系统。这种方法包括两个阶段：关闭时间和开启时间。在关闭时间，在开启时间阶段实施训练神经网络，重新配置缓存使用神经网络学习方法来预测正在运行的应用程序所需的延迟。具有 64 核的三维芯片的实验结果表明，与不可重构的纯 SRAM 缓存架构相比，在 PARSEC 基准测试下的建议设计在性能方面提供了 25% 的加速，并将能耗降低了 78.4%。