Planar metal-insulator-semiconductor capacitors are fabricated on native gallium nitride substrates with different gate dielectrics, namely, silicon dioxide, silicon nitride, and aluminum oxide. The leakage current was measured to determine their robustness regarding electrical breakdown. Hysteresis effects were evaluated for the different gate dielectrics and for the substrate and the epitaxial surface. A gate-first process with a gate contact made from poly-crystalline silicon was compared to a gate-last process with a sputtered aluminum gate. The former showed superior robustness against electrical breakdown with a dielectric breakdown field strength of ≈ 9 MV/cm, which was found to be mostly independent of temperature in the range of 250–450 K. Furthermore, gate oxide traps were estimated by means of stress/recovery gate current transient measurements to confirm field strength limits for high lifetime requirements. Based on the various measurements, silicon dioxide emerged as the best choice regarding breakdown robustness and hysteresis effects. A limit for the dielectric field strength of 3–4 MV/cm is proposed to avoid short- and long-term damage of the dielectric layer.

中文翻译：

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用于具有高寿命要求的应用的原生氮化镓衬底上的金属绝缘体半导体电容器的栅极工程

平面金属-绝缘体-半导体电容器制造在具有不同栅极电介质（即二氧化硅、氮化硅和氧化铝）的原生氮化镓衬底上。测量泄漏电流以确定它们在电击穿方面的稳健性。对不同栅极电介质以及衬底和外延表面的滞后效应进行了评估。将具有由多晶硅制成的栅极触点的先栅极工艺与具有溅射铝栅极的后栅极工艺进行比较。前者显示出优异的抗电击穿鲁棒性，介电击穿场强约为 9 MV/cm，被发现主要与 250-450 K 范围内的温度无关。此外，通过应力/恢复栅极电流瞬态测量来估计栅极氧化物陷阱，以确认高寿命要求的场强限制。根据各种测量结果，二氧化硅成为击穿稳健性和滞后效应的最佳选择。建议将介电场强限制为 3-4 MV/cm，以避免介电层的短期和长期损坏。