The design, fabrication, and characterization of single metal gate layer, metal-oxide-semiconductor (MOS) quantum dot devices robust against dielectric breakdown are presented as prototypes for future diagnostic qubits. These devices were developed as a preliminary solution to a longer term goal of a qubit platform for intercomparison between materials or for in-line diagnostics and to provide a testbed for establishing classical measurements predictive of coherence performance. For this stage, we seek a robust MOS design that is compatible with wafer and chip architectures, which has a reduced process overhead and is sufficiently capable of challenging and advancing our measurement capabilities. In this report, we present our initial batch of silicon MOS devices using a single gate layer, which have not exhibited any failures with gate voltage excursions $>10$ V but do exhibit the reduced electrostatic control expected of a single gate layer design. We observe quantum dot formation, capacitive charge sensing between channels, and reasonable effective electron temperatures that enable spin qubit studies. The costs and benefits of the trade-off between device performance and fabrication efficiency will be discussed, as well as opportunities for future improvements.

中文翻译：

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开发用于诊断量子位的单层金属氧化物半导体量子点

单金属栅极层、金属氧化物半导体 (MOS) 量子点器件的设计、制造和表征对介电击穿具有鲁棒性，作为未来诊断量子位的原型。这些设备的开发是作为量子位平台长期目标的初步解决方案，用于材料之间的相互比较或在线诊断，并为建立预测相干性能的经典测量提供测试平台。在此阶段，我们寻求与晶圆和芯片架构兼容的稳健 MOS 设计，该设计具有降低的工艺开销，并且足以挑战和提升我们的测量能力。在本报告中，我们展示了使用单栅极层的第一批硅 MOS 器件，$>10$ V 但是确实表现出单栅极层设计所期望的降低的静电控制。我们观察到量子点的形成、通道之间的电容性电荷感应以及合理的有效电子温度，从而能够进行自旋量子位研究。将讨论设备性能和制造效率之间权衡的成本和收益，以及未来改进的机会。