In this work, drain current I_D for 3 nm gate length of triple material (TM) double surrounding gate (DSG) inversion mode (IM) and junctionless (JL) Si nanotube (SiNT) MOSFET has been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device we consider the Non Equilibrium Green’s Function (NEGF) approach and self-consistent solution of Poisson’s equation with Schrodinger’s equation. The channel region is lightly doped in case of IM SiNT MOSFET. The effect of TM Gate Engineering for SiNT channel radius 1.5 nm and gate oxide (SiO₂) thickness of 0.8 nm on I_D, has been studied. Also comparison of results has been done between IM TM DSG and JL TM DSG SiNT. For a reasonable comparison between Junctionless and Inversion Mode SiNT, in Junctionless SiNT, doping concentration is optimized for two concerns (i) to get the same threshold voltage (V_TH) as IM SiNT and (ii) to get the same I_ON current as IM SiNT MOSFET. This results in 10³ times smaller I_OFF in both matching V_TH and I_ON optimized device as compared to IM SiNT MOSFET. It was found that TM Gate Engineering reduces drain induced barrier lowering (DIBL) in JL SiNT. JL SiNT MOSFET has a smaller DIBL ~ 61.02 mV/V, almost an ideal SS ~ 60 mV/dec and higher I_ON/I_OFF ratio ~ 2.63 × 10⁹ as compared to available CGAA literature device results.

在这项工作中，研究了三层材料（TM），双环绕栅（DSG）反转模式（IM）和无结（JL）硅纳米管（SiNT）MOSFET的3 nm栅极长度的漏极电流I _D，并报告了使用的仿真结果Silvaco ATLAS 3D TCAD。在该设备中，我们考虑了非平衡格林函数（NEGF）方法和带有Schrodinger方程的Poisson方程的自洽解。对于IM SiNT MOSFET，沟道区域是轻掺杂的。TM门工程为SINT通道半径为1.5nm和栅极氧化物的效果（SIO ₂）上的0.8纳米厚我_d，已被研究。IM TM DSG和JL TM DSG SiNT之间也进行了结果比较。为了在无结SiNT和反转模式SiNT之间进行合理比较，在无结SiNT中，针对以下两个方面优化了掺杂浓度：（i）获得与IM SiNT相同的阈值电压（V _TH），以及（ii）获得与IM SiNT相同的I _ON电流。 IM SiNT MOSFET。这_使得匹配的V _TH和I _ON的I _OFF减小10 ³倍与IM SiNT MOSFET相比，该器件具有最佳性能。已经发现，TM Gate Engineering减少了JL SiNT中的漏极诱导势垒降低（DIBL）。与可用的CGAA文献器件结果相比，JL SiNT MOSFET的DIBL较小，约为61.02 mV / V，理想SS约为60 mV / dec，I _ON / I _OFF比率较高，约为2.63×10 ⁹。