We describe challenges of the epitaxial Si-cap/Si_0.75Ge_0.25//Si-substrate growth process, in view of its application in 3D device integration schemes using Si_0.75Ge_0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si_0.75Ge_0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-growth on top of strained Si_0.75Ge_0.25, even for thinner Si_0.75Ge_0.25 layers and when growing the Si-cap layer at a lower temperature. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap/Si_0.75Ge_0.25//Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer-to-wafer bonding and Si-substrate and Si_0.75Ge_0.25 backside removal.

考虑到外延Si-cap / Si _0.75 Ge _0.25 // Si衬底生长工艺的挑战，鉴于其在使用Si _0.75 Ge _0.25作为背面蚀刻停止层的3D器件集成方案中的应用，重点是高产量Epi处理而不影响材料质量。尽管可以生长厚度大于理论厚度10倍的全应变Si _0.75 Ge _0.25以便进行层弛豫，但要完全避免在应变Si _0.75 Ge _0.25上方进行Si生长过程中完全避免晶片边缘的错位错位是有挑战性的，甚至更薄的Si _0.75 Ge _0.25在较低的温度下生长硅盖层时。必须使用极其灵敏的表征方法来检测晶圆边缘错位错位的极低密度。光散射测量是最可靠的。外延的Si-cap / Si _0.75 Ge _0.25 // Si衬底叠层对于典型的在晶片间键合以及Si衬底和Si _0.75 Ge _0.25背面去除之前的后后热处理步骤是稳定的。