In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order interpolation based nonlinearity calibration is proposed. Besides, the static phase offsets (SPO) between bang-bang phase detector (BBPD) and multiplexer (MUX) are calibrated by a proposed hybrid analog/digital phase offset calibration, while the dynamic phase offsets (DPO) are removed by a proposed complementary switching scheme. The co-design of the analog circuits and digital calibrations enable excellent jitter and spur performance. The MDLL achieves 0.70 and 0.48ps root-mean-square (RMS) jitter in fractional-N and integer-N modes, respectively. The fractional spur is less than -59.0dBc, and the reference spur is -64.5dBc. The power consumptions are 1.85mW and 1.22mW, corresponding to figures of merit (FOM) of -240.4dB and -245.5dB.

中文翻译：

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具有基于零阶插值的 DTC 非线性校准和两步混合相位偏移校准的完全可合成分数 N MDLL


本文提出了一种基于全合成数字时间（DTC）的分数N乘法延迟锁定环（MDLL）。分析了可综合DTC的噪声和线性度，提出了一种两级可综合DTC，其中路径选择DTC用作粗级，可变斜率DTC用作细级。为了校准 DTC 非线性，提出了一种高度鲁棒的基于零阶插值的非线性校准。此外，通过提出的混合模拟/数字相位偏移校准来校准开关式相位检测器（BBPD）和多路复用器（MUX）之间的静态相位偏移（SPO），而动态相位偏移（DPO）则通过提出的互补相位偏移来消除。切换方案。模拟电路和数字校准的共同设计可实现出色的抖动和杂散性能。 MDLL 在小数 N 模式和整数 N 模式下分别实现 0.70 和 0.48ps 均方根 (RMS) 抖动。分数杂散小于-59.0dBc，参考杂散为-64.5dBc。功耗分别为1.85mW和1.22mW，对应的品质因数(FOM)为-240.4dB和-245.5dB。