An analytical approach to evaluate performance of analog integrated circuits and make a comparative study in different technology nodes is presented. To provide closed-form solutions, this article proposes using $\mathscr {C} = \text {C}/\text {I}_{\text {DS}}$ as an independent design variable, where C refers to any physical or parasitic capacitance associated with a Field-Effect Transistor (FET) biased at I_DS. The proposed $\mathscr {C}$ -based methodology is used to study speed versus power trade-offs in both continuous-time (CT) and discrete-time (DT) circuits. Predictive Technology Models (PTMs) have been used to study performance of both MOSFET and FinFET (i.e. FET) devices in different technology nodes. This analysis shows that FinFET transistors exhibit a wider medium-inversion region compared to MOSFET devices, making them more convenient for high-speed and low-power designs. Additionally, this study proves that a lower sub-threshold slope factor results in an improved energy-efficiency of analog circuits.

中文翻译：

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使用 C/IDS 方法设计按比例缩放的 FET 电路时的功率-速度权衡

提出了一种评估模拟集成电路性能并在不同技术节点中进行比较研究的分析方法。为了提供封闭形式的解决方案，本文建议使用 $\mathscr {C} = \text {C}/\text {I}_{\text {DS}}$ 作为一个独立的设计变量，其中 C 是指与偏置于 I _{DS 的}场效应晶体管 (FET) 相关的任何物理或寄生电容。拟议的 $\mathscr {C}$ 基于 的方法用于研究连续时间 (CT) 和离散时间 (DT) 电路中速度与功率的权衡。预测技术模型 (PTM) 已被用于研究不同技术节点中 MOSFET 和 FinFET（即 FET）器件的性能。该分析表明，与 MOSFET 器件相比，FinFET 晶体管具有更宽的中反转区，使其更适合高速和低功耗设计。此外，该研究证明，较低的亚阈值斜率因子可提高模拟电路的能效。