In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology.

中文翻译：

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折叠MOS电流模式逻辑中低压功率高效分频器的设计

在本文中，我们提出了一种基于低压折叠 MOS 电流模式逻辑 (FMCML) 方法来设计高速、节能静态分频器的方法。介绍了一种建模策略，用于分析传播延迟和功耗对 2 分频 (DIV2) 单元偏置电流的依赖性。我们证明 FMCML DIV2 单元的行为不同于传统的 MCML DFF（D 型触发器）和没有电平转换器的 FMCML DFF。然后提出了在不同设计场景下优化分频器的分析策略：最大速度、最小功率延迟积 (PDP) 或最小能量延迟积 (EDP)。还研究了在不影响速度性能的情况下缩放通过分压器级的偏置电流的可能性。建议的分析方法允许深入了解电路行为并全面优化不同的设计权衡。衍生模型和设计指南针对参考商用 28 纳米 FDSOI CMOS 工艺的晶体管级模拟进行了验证。在相同的 28nm CMOS 技术中设计了遵循不同优化策略的不同 8 分电路，显示了所提出方法的有效性。