A 28.8-GB/s 96-MB 3D-stacked SRAM is presented. A total of eight SRAM dies, designed in a 40-nm CMOS process, are vertically stacked and connected using an inductive coupling wireless link with a low-voltage NMOS push-pull transmitter that reduces the power of the link by 35% with a 0.4-V power supply. The SRAM utilizes an inverted bit insertion scheme that compensates for the degradation of the first transmitted bit, a coil termination scheme that aims to eliminate the ringing of 3D inductive coupling bus, and a 12:1 SerDes that minimizes power consumption and area overhead in inductive coupling channels. Low-power, large-capacity, 3-cycle latency 3D-stacked SRAM for a DNN accelerator is achieved with the combination of these techniques to serve as a replacement of 3D-stacked DRAM. The performance of the proposed 3D-SRAM is compared with HBM DRAM and achieves more than 50% lower energy consumption. The scaling scenario of the SRAM module is discussed in light of the scaling of the inductive coupling technology and logic process.

中文翻译：

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96MB 3D 堆叠 SRAM 使用电感耦合与 0.4V 发送器、端接方案和 40-nm CMOS 中的 12:1 SerDes

展示了一个 28.8-GB/s 的 96-MB 3D-stacked SRAM。共有 8 个 SRAM 芯片，采用 40 纳米 CMOS 工艺设计，垂直堆叠并使用电感耦合无线链路与低压 NMOS 推挽式发射器连接，使用 0.4 -V 电源。SRAM 采用反向位插入方案来补偿第一个传输位的退化，线圈端接方案旨在消除 3D 电感耦合总线的振铃，以及 12:1 SerDes 最大限度地减少电感中的功耗和面积开销。耦合通道。通过结合这些技术，实现了用于 DNN 加速器的低功耗、大容量、3 周期延迟的 3D 堆叠 SRAM，以替代 3D 堆叠 DRAM。所提出的 3D-SRAM 的性能与 HBM DRAM 相比，能耗降低了 50% 以上。根据电感耦合技术和逻辑过程的缩放来讨论SRAM模块的缩放场景。