In the generalized spatial modulation (GenSM) multiple input multiple output (MIMO) system, each block of data bits is mapped to a set of spatially multiplexed (SMX) symbols and an index of transmit antenna combination (TAC) of active antennas. The difficulty for the GenSM MIMO receiver is to detect the SMX symbols and TAC index simultaneously. Recently, we applied the conventional sphere decoding algorithm (SDA) successively to achieve the exact maximum likelihood detection (MLD) of GenSM MIMO signals. The SDA scheme suffers from variable computational complexity and leads to hardware detectors with variable throughput rate. Instead, fixed-complexity tree search algorithms, e.g., reduced fixed sphere decoding (rFSD), with nearly MLD performance are employed to facilitate hardware implementation. Here, we propose to apply the rFSD successively and design a hardware architecture for detecting GenSM MIMO signals under the scenario of 5 transmit antennas, 2 transmit radio frequency chains, 4 receive antennas, and 64-QAM SMX symbols. The VLSI implementation results under the TSMC 90nm CMOS technology reveal that our architecture requires 276.7K gates and provides detection throughput 1.613 Gbps, while operating at 322.6 MHz. Compared with other related architectures, our architecture provides higher detection throughput rate and is of better hardware efficiency.

中文翻译：

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用于检测广义空间调制信号的固定复杂度树搜索方案：算法和硬件架构

在广义空间调制 (GenSM) 多输入多输出 (MIMO) 系统中，每个数据位块都映射到一组空间复用 (SMX) 符号和有源天线的发射天线组合 (TAC) 索引。GenSM MIMO 接收器的难点在于同时检测 SMX 符号和 TAC 索引。最近，我们相继应用了传统的球形解码算法（SDA）来实现对 GenSM MIMO 信号的精确最大似然检测（MLD）。SDA 方案受制于可变的计算复杂性并导致硬件检测器具有可变的吞吐率。取而代之的是，采用具有接近 MLD 性能的固定复杂度树搜索算法，例如简化的固定球体解码 (rFSD)，以促进硬件实现。这里，我们建议在 5 个发射天线、2 个发射射频链、4 个接收天线和 64-QAM SMX 符号的场景下，依次应用 rFSD 并设计用于检测 GenSM MIMO 信号的硬件架构。TSMC 90nm CMOS 技术下的 VLSI 实现结果表明，我们的架构需要 276.7K 门，并提供 1.613 Gbps 的检测吞吐量，同时以 322.6 MHz 运行。与其他相关架构相比，我们的架构提供了更高的检测吞吐率和更好的硬件效率。TSMC 90nm CMOS 技术下的 VLSI 实现结果表明，我们的架构需要 276.7K 门，并提供 1.613 Gbps 的检测吞吐量，同时以 322.6 MHz 运行。与其他相关架构相比，我们的架构提供了更高的检测吞吐率和更好的硬件效率。TSMC 90nm CMOS 技术下的 VLSI 实现结果表明，我们的架构需要 276.7K 门，并提供 1.613 Gbps 的检测吞吐量，同时以 322.6 MHz 运行。与其他相关架构相比，我们的架构提供了更高的检测吞吐率和更好的硬件效率。