In this paper, we propose an efficient and promising soft error tolerance approach for arithmetic circuits with high performance and low area overhead. The technique is applied for designing soft error tolerant adders and is based on the use of a fault tolerant C-element connecting a given adder output to one input of the C-element while connecting a delayed version of that output to the second input. It exploits the variability of the delay of the adder output bits, in which the most significant bits (MSBs) have longer delay than the least significant bits (LSBs), by adding larger delay to the LSBs and smaller delay to the MSBs to guarantee full fault tolerance against the largest pulse width of transient error (soft error) for the available technology with minimum impact on performance. To guarantee fault protections for transistors feeding outputs with smaller added delay, the technique utilizes transistor scaling to ensure that the injected fault pulse width is less than the added delay of the second output of the C-element. Simulation results reveal that the proposed technique takes precedence over other techniques in terms of failure rate, area overhead, and delay overhead. The evaluation experiments have been done based on simulations at the transistor level using HSPICE to take care of temporal masking combined with electrical masking. In comparison to TMR, the technique achieves 100% reliability with 31% reduction in area overhead without impacting performance in the case of a 32-bit adder, and 42% reduction in area overhead and 5% reduction in performance overhead in the case of a 64-bit adder. While our proposed technique achieves area reduction of 4.95% and 9.23% in comparison to CE-based DMR and Feedback-based DMR techniques in the case of a 32-bit adder, it achieves area reduction of 19.58% and 23.24% in the case of a 64-bit adder.

在本文中，我们为具有高性能和低面积开销的算术电路提出了一种有效且有前途的软容错方法。该技术用于设计软容错加法器，并且基于使用容错C元素将给定加法器输出连接到C元素的一个输入，同时将该输出的延迟版本连接到第二个输入。它利用加法器输出位的延迟可变性，其中最高有效位（MSB）的延迟比最低有效位（LSB）更长，这是通过向LSB添加更大的延迟，并向MSB添加较小的延迟来保证的。针对现有技术的最大瞬态误差（软误差）脉冲宽度的容错能力，对性能的影响最小。为了保证以较小的附加延迟为输出供电的晶体管提供故障保护，该技术利用晶体管缩放比例来确保注入的故障脉冲宽度小于C元素第二个输出的附加延迟。仿真结果表明，所提出的技术在故障率，面积开销和延迟开销方面比其他技术要优先。已经基于使用HSPICE在晶体管级进行的仿真来完成评估实验，以照顾与电屏蔽相结合的时间屏蔽。与TMR相比，该技术实现了100％的可靠性，在32位加法器的情况下，面积开销减少了31％，而又不影响性能；在32位加法器的情况下，面积开销减少了42％，性能开销减少了5％。 64位加法器。