This study investigates the effect of the gate SiO₂ thickness (80, 100, and 130 nm) deposited by plasma enhanced chemical vapor deposition on the interface and reliability characteristics of low-temperature polycrystalline silicon thin film transistors. Field effect mobility is significantly degraded as the gate oxide thickness decreases. The border trap density (N_bt) extracted from capacitance–voltage hysteresis exhibits no trend with respect to the gate oxide thickness, indicating that field effect mobility is not governed by N_bt. The quantitative interface trap density (N_it) was obtained using a 3-terminal charge pumping method; results showed that N_it decreased as the gate oxide thickness increased. However, it was observed that the threshold voltage (V_th) shift during negative bias temperature stress is worse in the thicker SiO₂ film, which has a low N_it. After activation annealing, the amount of hydrogen in the gate oxide increased as the thickness of the insulator was raised. This in turn caused a larger shift in V_th. To validate this mechanism, the amount of hydrogen with respect to the device depth was analyzed via secondary ion mass spectroscopy. It has been found that the presence of more hydrogen concentration in the SiO₂ film and the interface to the thicker SiO₂ results in more V_th shifts under bias temperature stress.

本研究研究了通过等离子体增强化学气相沉积法沉积的栅极SiO ₂厚度（80、100和130 nm）对低温多晶硅薄膜晶体管的界面和可靠性特性的影响。随着栅极氧化物厚度的减小，场效应迁移率显着降低。从电容-电压迟滞提取的边界陷阱密度（N _bt）相对于栅极氧化物厚度没有任何趋势，表明场效应迁移率不受N _bt的控制。使用三端电荷泵方法获得定量的界面陷阱密度（N _it）。结果表明，_它随着栅极氧化物厚度的增加而减小。然而，已经观察到，在负偏置温度应力期间的阈值电压（V _th）在具有较低N _it的较厚的SiO ₂膜中较差。活化退火后，随着绝缘体厚度的增加，栅氧化层中的氢含量增加。反过来，这引起了V _th的较大偏移。为了验证该机理，通过二次离子质谱法分析了相对于器件深度的氢气量。已经发现，在SiO ₂膜中存在更多的氢浓度以及与更厚的SiO ₂的界面会导致更大的V _th。 在偏置温度应力下移动。