An analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a two-stage programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) merged by a pipelined analog–digital converter (ADC), and a digital-analog converter (DAC). Compared with conventional readout architecture, the proposed can provide finer gain, level shifting as well as offset calibrating function. A 1.5-Mpixel 60-fps CIS with the ASP is fabricated in a 0.13 μm 1P4M CMOS mixed signal process. The experiment results indicate the sensor can normally capture images without missing code. Moreover, the measured maximum gain error of the PGA is 1.6%, and the power dissipation is 16.5 mW for single ASP.

提出了用于CMOS图像传感器（CIS）读出的模拟信号处理（ASP）电路。拟议中的ASP主要包括两级可编程增益放大器（PGA），由流水线模数转换器（ADC）合并的采样保持放大器（SHA）和数模转换器（DAC）。与传统的读出架构相比，该提议可以提供更好的增益，电平移位以及失调校准功能。采用0.13μm1P4M CMOS混合信号工艺制造具有ASP的1.5像素60 fps CIS。实验结果表明该传感器可以正常捕获图像而不会丢失代码。此外，测得的PGA的最大增益误差为1.6％，单个ASP的功耗为16.5 mW。