A major role is played by Modeling and Simulation platforms in development of a new Network-on-Chip (NoC) architecture. The cycle accurate software simulators tend to become slow when simulating thousands of cores on a single chip. FPGAs have become the vehicle for simulation acceleration due to the properties of parallelism. Most of the state-of-the-art FPGA based NoC simulators utilize soft logic only for modeling the NoCs, leaving out the hard blocks to be unutilized. In this work, the FIFO Buffer and Crossbar switch functionalities of the NoC router have been embedded in the Block RAM (BRAMs) and the DSP48E1 slices with large multiplexer respectively. Employing the proposed techniques of mapping the NoC router components on the FPGA hard blocks, an NoC simulation acceleration framework based on the FPGA is presented in this work. A huge reduction in the use of the Configurable Logic Blocks (CLBs) has been observed when the FIFO buffer and Crossbar components of the NoC topology’s router micro-architecture are embedded in FPGA hard blocks. Our experimental results show that the topologies implemented employing the proposed FPGA friendly mapping of the NoC router components on the hard blocks consume 43.47% fewer LUTs and 41.66% fewer FFs than the topologies with CLB implementation. To optimize the latency of the NoC under consideration, a control unit called “buf_empty_checker” has been employed. A reduction in average latency has been observed compared to the CLB based topology implementation employing the proposed mapping. The proposed work consumes 10.88% fewer LUTs than the CONNECT NoC generation tool. Compared to DART, a reduction of 73.38% and 66.55% in LUTs and FFs has been observed with respect to the proposed work. The average packet latency of the proposed NoC architecture is 24.8% and 19.1% lesser than the CONNECT and DART architectures.

建模和仿真平台在开发新的片上网络（NoC）架构中扮演着重要角色。当在单个芯片上模拟数千个内核时，周期精确的软件模拟器往往会变慢。由于并行性，FPGA已成为仿真加速的工具。大多数基于FPGA的最先进的NoC仿真器仅将软逻辑用于NoC建模，而没有使用硬模块。在这项工作中，NoC路由器的FIFO缓冲区和交叉开关功能已分别嵌入到具有大型多路复用器的Block RAM（BRAM）和DSP48E1 slice中。利用所提出的将NoC路由器组件映射到FPGA硬块上的技术，本文提出了一种基于FPGA的NoC仿真加速框架。当将NoC拓扑的路由器微体系结构的FIFO缓冲区和Crossbar组件嵌入到FPGA硬模块中时，可以观察到可配置逻辑模块（CLB）的使用大大减少。我们的实验结果表明，与采用CLB实现的拓扑相比，在硬块上采用建议的FPGA友好的NoC路由器组件映射实现的拓扑消耗的LUT减少了43.47％，FF减少了41.66％。为了优化所考虑的NoC的等待时间，已经采用了称为“ buf_empty_checker”的控制单元。与采用建议的映射的基于CLB的拓扑实现相比，已观察到平均等待时间的减少。与CONNECT NoC生成工具相比，拟议的工作消耗的LUT减少了10.88％。与DART相比，减少了73.38％和66。在拟议工作中，已观察到55％的LUT和FF。提议的NoC架构的平均数据包延迟比CONNECT和DART架构低24.8％和19.1％。