An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm² and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

中文翻译：

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使用循环游标TDC进行突发模式链接的快速锁定全数字MDLL

提出了一种基于全数字乘法延迟锁定环（MDLL）的时钟倍增器，该时钟倍增器具有时间数字转换器（TDC）以实现快速上电能力。拟议的MDLL采用新的无偏移循环Vernier TDC，以实现15个参考时钟周期的快速锁定时间，同时保持较宽的检测范围和高分辨率。提议的无偏移TDC还使用相关的双采样技术来消除失配和偏移问题，从而降低了抖动特性。快速锁定MDLL之后，TDC将关闭，并进入基于delta-sigma调制器（DSM）的顺序跟踪模式，以降低功耗并改善抖动性能。拟议的MDLL以65 nm 1.0V CMOS工艺实现，占用0.043 mm ²的有效面积并从75MHz参考时钟产生一个2.4GHz输出时钟（倍频系数N = 32）。它实现了9.4 ps的有效峰峰值抖动，在2.4 GHz时的功耗为3.3 mW。