Electrostatic discharge (ESD) events can severely damage miniature components. Therefore, ESD protection is critical in integrated circuits. In this study, drain-electrode-embedded horizontal Schottky diode contact modulation and Schottky length reduction modulation were performed on a high-voltage 60-V n-channel laterally diffused metal-oxide–semiconductor transistor (nLDMOS) element. The effect of the on-voltage characteristics of cascade Schottky diodes on ESD protection was investigated. By using a transmission-line pulse tester, the trigger voltage, holding voltage, and secondary breakdown current (I_t2) of the nLDMOS element were determined using the I–V characteristic. As the N⁺ area was gradually replaced by the parasitic Schottky area at the drain electrode, an equivalent circuit of series Schottky diodes formed, which increased the on-resistance. The larger the Schottky area was the higher the I_t2 value was. This characteristic can considerably improve the ESD immunity of nLDMOS components (highest improvement of 104%). This is a good strategy for improving ESD reliability without increasing the production steps and fabrication cost.

中文翻译：

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HV nLDMOS漏极嵌入式水平肖特基元件的ESD设计与分析

静电放电（ESD）事件可能会严重损坏微型组件。因此，ESD保护在集成电路中至关重要。在这项研究中，在高压60V n沟道横向扩散的金属氧化物半导体晶体管（nLDMOS）元件上执行了嵌入漏极电极的水平肖特基二极管接触调制和肖特基长度减小调制。研究了级联肖特基二极管的导通电压特性对ESD保护的影响。通过使用传输线脉冲测试仪，利用I–V特性确定nLDMOS元件的触发电压，保持电压和二次击穿电流（I _t2）。作为N ⁺漏极上的寄生肖特基区域逐渐取代了该区域，形成了串联的肖特基二极管的等效电路，从而增加了导通电阻。肖特基面积越大，I _t2值越高。该特性可以显着提高nLDMOS组件的ESD抗扰性（最高提高104％）。这是在不增加生产步骤和制造成本的情况下提高ESD可靠性的好策略。