A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in the form of a sheet. The mNS-FET has superior gate controllability for the stacked channels; consequently, it can significantly reduce the short-channel effect (SCE); however, punch-through inevitably occurs in the bottom channel portion that is not surrounded by gates, resulting in a large leakage current. Moreover, as the size of the semiconductor device decreases to several nanometers, the influence of the parasitic resistance and parasitic capacitance increases. Therefore, it is essential to apply design–technology co-optimization, which analyzes not only the characteristics from the perspective of the device but also the performance from the circuit perspective. In this study, we used Technology Computer Aided Design (TCAD) simulation to analyze the characteristics of the device and directly fabricated a model that describes the current–voltage and gate capacitance characteristics of the device by using Berkeley short-channel insulated-gate field-effect transistor–common multi-gate (BSIM–CMG) parameters. Through this model, we completed the Simulation Program with Integrated Circuit Emphasis (SPICE) simulation for circuit analysis and analyzed it from the viewpoint of devices and circuits. When comparing the characteristics according to the presence or absence of bottom oxide by conducting the above research method, it was confirmed that subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are improved, and power and performance in circuit characteristics are increased.

中文翻译：

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亚纳米技术节点的多纳米晶体管的器件和电路探索

开发了多纳米片场效应晶体管（mNS-FET）器件，以最大程度地控制栅极，同时将沟道制成片状。mNS-FET对堆叠的通道具有出色的栅极可控性；因此，它可以显着降低短信道效应（SCE）；然而，在没有被栅极围绕的底部沟道部分中不可避免地发生穿通，从而导致大的泄漏电流。此外，随着半导体器件的尺寸减小到几纳米，寄生电阻和寄生电容的影响增加。因此，应用设计技术协同优化至关重要，该技术不仅从器件的角度分析特性，而且从电路的角度分析性能。在这个研究中，我们使用技术计算机辅助设计（TCAD）仿真来分析该器件的特性，并使用Berkeley短通道绝缘栅场效应晶体管-常见的方法直接构建了一个描述该器件的电流-电压和栅极电容特性的模型多门（BSIM–CMG）参数。通过该模型，我们完成了带有集成电路重点的仿真程序（SPICE）仿真，用于电路分析，并从器件和电路的角度对其进行了分析。通过进行上述研究方法，根据底部氧化物的有无来比较特性时，可以确认亚阈值斜率（SS）和漏极引起的势垒降低（DIBL）得到改善，电路特性的功率和性能提高。 。