In this paper, a novel partial product generation (PPG) scheme has been proposed based on the shift and the add logic of multiplier bits to introduce a radix-4 and radix-16 signed binary multiplications (SBMs). The proposed PPG methodology encodes two bits for radix-4 and four bits for radix-16 at a time, whereas the traditional modified Booth encoding (MBE) for radix-4 and radix-16 encodes three bits and five bits, respectively, at a time, which offers the reduction of the encoder combinations. In the proposed design, the multiplication sign extension is pre-decided from the most significant bit (MSB) of the multiplier and the multiplicand, thereby subtraction operation for multiplication is removed from traditional MBE. The simulation results of the proposed SBMs architecture offer a significant improvement in power, delay and power-delay-product (PDP). The PDP was reduced by ∼79%, ∼84% and ∼85%, respectively, with proposed radix-4 SBM and by ∼45%, ∼64% and ∼72%, respectively, with proposed radix-16 SBM for 8×8-,16×16-, and 32×32-bit multiplication, respectively, when compared with the existing state-of-the-art designs.

中文翻译：

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通过新的部分乘积生成方案改进有符号二进制乘法器

在本文中，提出了一种新颖的部分乘积生成 (PPG) 方案，该方案基于乘法器位的移位和加法逻辑，以引入 radix-4 和 radix-16 有符号二进制乘法 (SBM)。所提出的 PPG 方法一次对 radix-4 和 radix-16 编码两个比特，而对 radix-4 和 radix-16 的传统修改布斯编码 (MBE) 分别编码三个比特和五个比特，在时间，这提供了编码器组合的减少。在所提出的设计中，乘法符号扩展是从乘法器的最高有效位（MSB）和被乘数中预先确定的，从而从传统的MBE中去除了乘法的减法运算。所提出的 SBM 架构的仿真结果显着提高了功耗，延迟和功率延迟积（PDP）。PDP 减少了～79%,～84％ 和～85%，分别使用建议的 radix-4 SBM 和～45%,～64％ 和～72%，分别与建议的 radix-16 SBM8×8-,16×16-， 和32×32位乘法，分别与现有的最先进的设计相比。