The advancement of next-generation systems has led to a rapid increase in day-to-day applications by connecting billions of devices. Mobile networks require a considerable cost to support these billions of devices, and conventional IEEE 802.11 is meant for the usage of small-scale applications. To support long-range applications, IEEE task group-ah has proposed a new standard named IEEE 802.11ah. However, it has challenges like efficient device grouping based on variable sampling rates and power consumption. This standard employs orthogonal frequency-division multiplexing as a multicarrier scheme that suffers from high peak-to-average power ratio (PAPR). Hence, to support multiple devices of variable rates in the physical layer along with low PAPR and acceptable bit error rate, a new framework and an optimized architecture of carrier interferometry-group orthogonal–orthogonal frequency-division multiple access architecture is proposed. The proposed architecture reduces the 16-point inverse fast Fourier transform area by 57.1%, device padding area by 50% along with three extra adders functional area compared with the existing architecture. Furthermore, the proposed architecture is prototyped on Virtex5 field-programmable gate array for on-chip validation, and the hardware parameters are measured in real time. The area-timing complexity of the proposed architecture is estimated and further achieves the lowest area- and power-delay product than the existing architecture. Application-specific integrated circuit implementation is carried out using commercially available 32 - nm technology library, where the postlayout results reported less area utilization and low power consumption.

中文翻译：

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用于 IEEE 802.11ah 的低 PAPR 多设备可变速率架构的 ASIC 实现

下一代系统的进步通过连接数十亿台设备导致日常应用程序的快速增加。移动网络需要相当大的成本来支持这数十亿台设备，而传统的 IEEE 802.11 旨在用于小规模应用的使用。为了支持远程应用，IEEE 任务组-ah 提出了一个名为 IEEE 802.11ah 的新标准。然而，它面临着基于可变采样率和功耗的高效设备分组等挑战。该标准采用正交频分复用作为受高峰均功率比 (PAPR) 影响的多载波方案。因此，为了在物理层支持多个可变速率设备以及低 PAPR 和可接受的误码率，提出了一种新的载波干涉测量组正交正交频分多址架构的框架和优化架构。与现有架构相比，所提出的架构将 16 点逆快速傅立叶变换区域减少了 57.1%，设备填充区域减少了 50%，以及三个额外的加法器功能区域。此外，所提出的架构在 Virtex5 现场可编程门阵列上进行原型验证，用于片上验证，并实时测量硬件参数。估计所提议架构的面积时序复杂度，并进一步实现比现有架构最低的面积和功率延迟乘积。使用商用 32-nm 技术库执行特定应用的集成电路实现，