Variable-rate transceivers, which adapt to the conditions, will be central to energy-efficient communication. However, fiber-optic communication systems with high bit-rate requirements make design of flexible transceivers challenging, since additional circuits needed to orchestrate the flexibility will increase area and degrade speed. We propose a variable-rate VLSI architecture of a forward error correction (FEC) decoder based on hard-decision product codes. Variable shortening of component codes provides a mechanism by which code rate can be varied, the number of iterations offers a knob to control the coding gain, while a key-equation solver module that can swap between error-locator polynomial coefficients provides a means to change error correction capability. Our evaluations based on 28-nm netlists show that a variable-rate decoder implementation can offer a net coding gain (NCG) range of 9.96–10.38dB at a post-FEC bit-error rate of $10\mathbf {^{-15}}$ . The decoder achieves throughputs in excess of 400Gb/s, latencies below 53ns, and energy efficiencies of 1.14pJ/bit or less. While the area of the variable-rate decoder is 31% larger than a decoder with a fixed rate, the power dissipation is a mere 5% higher. The variable error correction capability feature increases the NCG range further, to above 10.5dB, but at a significant area cost.

中文翻译：

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用于 400 Gb/s 硬判决乘积解码器的可变速率 VLSI 架构

适应条件的可变速率收发器将成为节能通信的核心。然而，具有高比特率要求的光纤通信系统使灵活收发器的设计具有挑战性，因为协调灵活性所需的额外电路会增加面积并降低速度。我们提出了一种基于硬判决乘积码的前向纠错 (FEC) 解码器的可变速率 VLSI 架构。组件代码的可变缩短提供了一种可以改变码率的机制，迭代次数提供了一个控制编码增益的旋钮，而一个可以在错误定位多项式系数之间交换的关键方程求解器模块提供了一种改变的方法纠错能力。我们基于 28 纳米网表的评估表明，可变速率解码器实现可以提供 9.96–10.38dB 的净编码增益 (NCG) 范围，FEC 后误码率为 $10\mathbf {^{-15} }$ 。解码器实现了超过 400Gb/s 的吞吐量、低于 53ns 的延迟以及 1.14pJ/bit 或更低的能效。虽然可变速率解码器的面积比固定速率的解码器大 31%，但功耗仅高出 5%。可变纠错能力特性进一步增加了 NCG 范围，达到 10.5dB 以上，但面积成本很大。虽然可变速率解码器的面积比固定速率的解码器大 31%，但功耗仅高出 5%。可变纠错能力特性进一步增加了 NCG 范围，达到 10.5dB 以上，但面积成本很大。虽然可变速率解码器的面积比固定速率的解码器大 31%，但功耗仅高出 5%。可变纠错能力特性进一步增加了 NCG 范围，达到 10.5dB 以上，但面积成本很大。