This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover- points distribution at the transitions introduces the single-loop phase tracking technique. In addition, low-power techniques at both the architecture and circuit levels are employed to greatly improve the overall energy efficiency and multiply data throughput by increasing the number of levels on the magnitude. Fabricated in 28-nm CMOS, our BBCDR prototype scores a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s under NRZ/PAM-4/PAM-8 modes, respectively. The jitter is < 0.53 ps (integrated from 100 Hz to 1 GHz) with approximately-equivalent constant loop bandwidth, and we achieve at least 1-UIpp jitter tolerance up to 10 MHz for all the three modes.

中文翻译：

---

28-nm CMOS 中的 0.14 至 0.29-pJ/位 1​​4-GBaud/s 三模式 (NRZ/PAM-4/PAM-8) 半速率 Bang-Bang 时钟和数据恢复 (BCDR) 电路

本文报告了一种支持三模态 (NRZ/PAM-4/PAM-8) 操作的半速率砰砰时钟和数据恢复 (BBCDR) 电路。在转换处观察它们的交叉点分布引入了单环相位跟踪技术。此外，在架构和电路层面均采用低功耗技术，通过增加数量级的数量来大大提高整体能效和成倍增加数据吞吐量。在 28 纳米 CMOS 中制造，我们的 BBCDR 原型在 NRZ/PAM-4/PAM-8 模式下分别在 14.4/28.8/43.2 Gb/s 下获得 0.29/0.17/0.14 pJ/bit 效率。抖动 < 0.53 ps（从 100 Hz 到 1 GHz 的积分），具有近似等效的恒定环路带宽，对于所有三种模式，我们在高达 10 MHz 的频率下实现了至少 1-UIpp 的抖动容限。