Reconfigurable FETs (RFETs) are ambipolar transistors featuring the ability to conduct both electrons and holes, which is often achieved through the use of silicon nanowires or similar gate-all-around topologies. In this article, we present initial results for standard cell synthesis based on our planar RFET device, featuring top-down planar silicon based technology, lower fabrication complexity than nanowire approaches and a high operating temperature robustness. We first introduce the device physics by explaining the structure and the operating principle on device level. We also summarize recent device optimizations to increase drive current and achieve symmetry between N- and P-type conduction. Next to CMOS-style standard cells, we present a reduced transistor count XOR cell and analyze timing. Transient simulations are performed entirely in TCAD to accurately show device performance. Further we describe extraction of relevant parameters of these circuits for usage in synthesis tools and compare our standard cells to a similar 180nmSOI technology. Afterwards we perform timing analysis for a full adder and explore the boundaries of our device with a larger cryptographic accelerator core.

中文翻译：

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从 MOSFET 到双极晶体管：平面 RFET 技术的标准单元合成

可重构 FET (RFET) 是双极晶体管，具有传导电子和空穴的能力，这通常通过使用硅纳米线或类似的环栅拓扑来实现。在本文中，我们展示了基于我们的平面 RFET 器件的标准单元合成的初步结果，该器件具有自顶向下的平面硅基技术、比纳米线方法更低的制造复杂性和高工作温度稳定性。我们首先通过在器件级解释结构和工作原理来介绍器件物理。我们还总结了最近的器件优化，以增加驱动电流并实现 N 型和 P 型传导之间的对称。在 CMOS 风格的标准单元旁边，我们展示了一个减少晶体管数量的 XOR 单元并分析了时序。瞬态模拟完全在 TCAD 中执行，以准确显示器件性能。我们进一步描述了这些电路的相关参数的提取以用于综合工具，并将我们的标准单元与类似的 180nmSOI 技术进行比较。之后，我们对全加器执行时序分析，并探索具有更大加密加速器内核的设备的边界。