This article presents a quarter-rate source-synchronous PAM-4 receiver for energy-efficient chip-to-module communication. A novel single-stage multiple peaking continuous-time linear equalizer (MP-CTLE) using feedback enabled multiple peaking scheme for both high-frequency equalization (HF-EQ) and low-frequency equalization (LF-EQ) is proposed to improve the BER performance and overall energy efficiency. The LF-EQ of the MP-CTLE eliminates the need for many DFE taps in SR/VSR applications to save power and area. A 1-tap feedforward equalizer (FFE) is used to further compensate for the high-frequency loss. We also use a ring oscillator based wide bandwidth phase-locked loop (WBW-PLL) as the multiphase clock generator (MPCG) in the clock and data recovery loop to save power with acceptable phase accuracy. Fabricated in 40-nm CMOS technology, the prototype receiver chip achieves error-free operation up to 52 Gb/s PAM-4 with superior bit efficiency of 0.126pJ/bit/s/dB while compensating 7.3-dB channel loss at 13GHz. With the proposed single-stage MP-CTLE, the receiver extends the error-free operation from PRBS-7 to PRBS-9. The BER bathtub curve at $10^{-6}$ is improved from 0.018 UI to around 0.1 UI.

中文翻译：

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用于40nm CMOS的52Gb / s Sub-1-pJ / bit PAM4接收器，用于低功耗互连

本文介绍了一种四分之一速率源同步PAM-4接收器，用于节能的芯片到模块通信。提出了一种新颖的单级多峰连续时间线性均衡器（MP-CTLE），该方案使用反馈使能的多峰方案同时实现高频均衡（HF-EQ）和低频均衡（LF-EQ），以提高BER性能和整体能源效率。MP-CTLE的LF-EQ消除了SR / VSR应用中许多DFE抽头的需要，从而节省了功率和面积。1抽头前馈均衡器（FFE）用于进一步补偿高频损耗。我们还使用基于环形振荡器的宽带锁相环（WBW-PLL）作为时钟和数据恢复环路中的多相时钟发生器（MPCG），从而以可接受的相位精度节省了功率。采用40纳米CMOS技术制造，原型接收器芯片可实现高达52 Gb / s PAM-4的无错误运行，具有0.126pJ / bit / s / dB的出色比特效率，同时在13GHz时可补偿7.3dB的信道损耗。利用所提出的单级MP-CTLE，接收器将无差错操作从PRBS-7扩展到PRBS-9。BER浴缸曲线位于 $ 10 ^ {-6} $ 从0.018 UI改进到约0.1 UI。