This article describes low latency, zero overhead DFE burst error correction technique. Without any encoder or decoder latency, the proposed technique makes use of the existing pre-cursor ISI to detect and correct errors on a burst of data. The implemented proof-of-concept 2-tap DFE prototype in 65nm CMOS operates at 16 Gb/s and compensates 32 dB loss consuming 58 mW only. With an additional 18 mW, the receiver enables error correction capability that translates to 2-to-6 dB SNR gain depending on the pre-cursor magnitude. Experimental results demonstrate that for lossy channels where pre-cursor is 60% or higher of main, this error correction outperforms RS(528, 514) without any overhead and with much lower latency and power consumption.

中文翻译：

---

决策反馈均衡中的低延迟突发错误检测和纠正

本文介绍了低延迟，零开销的DFE突发纠错技术。在没有任何编码器或解码器延迟的情况下，所提出的技术利用现有的前体ISI来检测和纠正数据突发中的错误。在65nm CMOS中实现的概念验证的2抽头DFE原型以16 Gb / s的速度运行，并且仅消耗58 mW即可补偿32 dB损耗。再加上18 mW的功率，接收器就可以实现纠错功能，根据前驱幅度将其转换为2至6 dB的SNR增益。实验结果表明，对于有损耗通道（前导信号为主信号的60％或更高），这种纠错性能优于RS（528，514），而没有任何开销，并且延迟和功耗低得多。