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Fast realization of 3D space-time correlation sea clutter of large-scale sea scene based on FPGA: from EM model to statistical model
IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing ( IF 4.7 ) Pub Date : 2021-01-01 , DOI: 10.1109/jstars.2020.3043272
Shuhao Zhang , Jinxing Li , Yachao Li , Pengbo Wei , Min Zhang

Memoryless nonlinear transform (MNLT) method was widely used in the statistical model for sea clutter simulations. When the radar scattering data sets were obtained, we can simulate large scene and long-time varying 3-D sea surface scattering using expended power spectral quickly and accurately. Compared with the personal computer platform, field-programmable gate array (FPGA) has the unique merit of energy efficiency, high performance and adaptability. In this article, we proposed a novel architecture for implementing the 3-D MNLT algorithm on FPGA using high-level synthesis. As the simulation size increases, the demand for storage resources will also increase rapidly, and the on-chip memory resource will be limited on FPGA. Aiming at these problems, we divided the 3-D space-time simulation into a 2-D spatial simulation and a 3-D temporal simulation, so that we can make full use of the off-chip memory. Our design employs multiple on-chip buffer structures to decrease the transfer time of internal and external data on the FPGA. We also design a dataflow inverse fast Fourier transform processing engine (PE). The dataflow implementation overlapped butterfly operation, increasing concurrency and the overall throughput of this PE. Experimental results show that we can obtain the same accuracy and higher efficiency on a Xilinx Zynq XC7Z100 SoC platform.

中文翻译:

基于FPGA的大尺度海景3D时空相关海杂波快速实现:从EM模型到统计模型

无记忆非线性变换(MNLT)方法被广泛应用于海杂波模拟的统计模型中。获得雷达散射数据集后,我们可以使用扩展功率谱快速准确地模拟大场景和长时间变化的 3-D 海面散射。与个人计算机平台相比,现场可编程门阵列(FPGA)具有能效高、性能好、适应性强的独特优点。在本文中,我们提出了一种使用高级综合在 FPGA 上实现 3-D MNLT 算法的新架构。随着仿真规模的增加,对存储资源的需求也将迅速增加,片上存储器资源将在FPGA上受到限制。针对这些问题,我们将 3-D 时空模拟分为 2-D 空间模拟和 3-D 时间模拟,以便我们可以充分利用片外存储器。我们的设计采用多个片上缓冲区结构来减少 FPGA 上内部和外部数据的传输时间。我们还设计了一个数据流逆快速傅立叶变换处理引擎 (PE)。数据流实现与蝶形运算重叠,增加了此 PE 的并发性和整体吞吐量。实验结果表明,我们可以在 Xilinx Zynq XC7Z100 SoC 平台上获得相同的精度和更高的效率。我们还设计了一个数据流逆快速傅立叶变换处理引擎 (PE)。数据流实现与蝶形运算重叠,增加了此 PE 的并发性和整体吞吐量。实验结果表明,我们可以在 Xilinx Zynq XC7Z100 SoC 平台上获得相同的精度和更高的效率。我们还设计了一个数据流逆快速傅立叶变换处理引擎 (PE)。数据流实现与蝶形运算重叠,增加了此 PE 的并发性和整体吞吐量。实验结果表明,我们可以在 Xilinx Zynq XC7Z100 SoC 平台上获得相同的精度和更高的效率。
更新日期:2021-01-01
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