This study proposes the design of a light to digital converter (LDC) for the long-time continuous monitoring of the photoplethysmography (PPG) signal. The design system incorporates a transimpedance amplifier (TIA), a delta-sigma modulator (DSM), and a decimation filter. The analog front-end circuit is implemented in the integrated chip with the chip area of 2.76 mm² and fabricated via TSMC T18 process. The standard supply voltage used for the experiment is 1.8 V. The measurement result shows that the TIA – 3 db gain is 100 dB gain and – 3 dB cutoff frequency is 110 kHz. The design delta-sigma modulator can achieve the signal to noise plus distortion ratio (SNDR) of 50 dB at – 10 dB of the input signal. The measured signal to spurious-free dynamic range (SFDR) of the DSM is 50 dB. The measured effective number of the bit is (ENOB) of 8.3 bits. The on-chip 4th order decimation filter is used herein to convert the one-bit output of the DSM to the multibit output with a down sampling rate of 64 Hz. The measured cutoff frequency of the decimation filter is 10 Hz, and the operating sampling frequency is 1280 samples/seconds. Therefore, the overall designed bandwidth of the design system is 10 Hz bandwidth. The power consumption of the whole circuit is less than 100 µW. The achieved bandwidth of 10 Hz is the best among all the reported to date.

这项研究提出了一种光数字转换器（LDC）的设计，用于长时间连续监测光电容积描记（PPG）信号。该设计系统包含一个跨阻放大器（TIA），一个delta-sigma调制器（DSM）和一个抽取滤波器。模拟前端电路在集成芯片中实现，芯片面积为2.76 mm ²并通过台积电T18工艺制造。实验使用的标准电源电压为1.8V。测量结果表明，TIA – 3 db增益为100 dB增益，– 3 dB截止频率为110 kHz。设计的delta-sigma调制器可以在输入信号为– 10 dB时达到50 dB的信噪比和失真比（SNDR）。DSM的无杂散动态范围（SFDR）的测量信号为50 dB。测量的有效位数为（ENOB）8.3位。本文使用片上四阶抽取滤波器将DSM的一位输出转换为64 Hz下采样率的多位输出。抽取滤波器的测量截止频率为10 Hz，工作采样频率为1280个样本/秒。因此，设计系统的整体设计带宽为10 Hz带宽。整个电路的功耗小于100 µW。迄今为止达到的10 Hz带宽是所有报告中最好的。