Decimal multiplication is the most common operation in arithmetic applications. This paper presents an area-efficient digit-by-digit decimal multiplier using a modified binary-coded decimal digit multiplier. In general, a Binary-Coded Decimal (BCD) digit multiplier consists of two kinds of block, namely binary multiplier, and Partial Product Binary-to-Decimal (PPBD) converter. In the BCD digit multiplier design, the binary multiplier produces the partial product output by multiplying the multiplier value along with multiplicand, and the PPBD converter used to convert the binary partial product into the decimal value. Instead of the binary multiplier, this paper proposes a constant multiplier design to generate binary partial product values. Here, the multiplier value considers as the constant value. Further, the proposed architectures design and implement using both Field-Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC). When compared with the existing methods, the implementation results show that the proposed design effectively reduces the area requirement and delay.

十进制乘法是算术应用中最常见的运算。本文提出了一种使用改进的二进制编码的十进制数字乘法器的面积有效的逐位十进制乘法器。通常，二进制编码的十进制（BCD）数字乘法器由两种块组成，即二进制乘法器和部分乘积二进制到十进制（PPBD）转换器。在BCD数字乘法器设计中，二进制乘法器通过将乘数值与被乘数相乘来产生部分乘积输出，然后使用PPBD转换器将二进制部分乘积转换为十进制值。代替二进制乘法器，本文提出了一种常数乘法器设计来生成二进制部分乘积值。在此，乘数值被认为是常数。进一步，所提出的体系结构使用现场可编程门阵列（FPGA）和专用集成电路（ASIC）进行设计和实现。与现有方法相比，实现结果表明所提出的设计有效地减少了面积需求和延迟。