A fully integrated high efficiency switched-capacitor (SC) DC-DC converter with pulse frequency modulation (PFM) control is presented. The small signal model of the multiphase-interleaving SC converter is given and it is verified through the simulation and the measurement results. For high efficiency, this design set the dominant pole at the output of the error amplifier (EA) and the 14-phase interleaving topology can push the non-dominant pole away from the Unit Gain Frequency (UGF) for the loop stability. By combining the flying-well and the deep n-well (DNW) isolation techniques, the proposed high-density MOS capacitor can reduce both the parasitic loss and the charge sharing loss of the converter. The conversion ratio of the converter is 2:1 under 3.3V power supply. This SC DC-DC converter is fabricated in the 40nm CMOS process. It obtains the peak efficiency of 86.2% and the output power-density of 226mW/mm². It maintains the efficiency above 80% from 8mA to 50mA load condition

提出了一种具有脉冲频率调制（PFM）控制的完全集成的高效开关电容器（SC）DC-DC转换器。给出了多相交错SC变换器的小信号模型，并通过仿真和测量结果进行了验证。为了获得高效率，此设计在误差放大器（EA）的输出端设置了主极点，并且14相交织拓扑可以将非主极点推离单位增益频率（UGF），以实现环路稳定性。通过结合飞阱和深n阱（DNW）隔离技术，所提出的高密度MOS电容器可以减少转换器的寄生损耗和电荷共享损耗。在3.3V电源下，转换器的转换率为2：1。此SC DC-DC转换器采用40nm CMOS工艺制造。²。在8mA至50mA的负载条件下，效率保持在80％以上