An improved topology for sub-THz radiation detection realized in 65 nm CMOS, including an on-chip antenna and using zero biasing is presented in this article. The topology is based on a differential Colpitts topology working in reverse-mode and leverages the nonlinearity with respect to vDS in subthreshold operation to rectify. The use of tuned inductors at the gates and sources of the transistor core create degenerative resonance feedback, which further enhances the responsivity while working with zero bias eliminates 1/f noise to improve the NEP. Measurements demonstrated a voltage responsivity as high as 2 kV/W with a 3 dB RF BW of at least 50 GHz centered at 315 GHz and a record NEP of down to 3.5 pW/√Hz, verified both at zero-IF and using chopping from 0.5 Hz up to 2 kHz. The chip occupies an area of 0.165 mm2 including pads.

中文翻译：

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65-nm CMOS 中的零偏置 J 波段天线耦合检测器

本文介绍了在 65 nm CMOS 中实现的亚太赫兹辐射检测的改进拓扑，包括片上天线和使用零偏置。该拓扑基于在反向模式下工作的差分 Colpitts 拓扑，并在亚阈值操作中利用与 vDS 相关的非线性进行整流。在晶体管核心的栅极和源极处使用调谐电感器会产生退化谐振反馈，这进一步增强了响应度，同时在零偏压下消除了 1/f 噪声以改善 NEP。测量结果表明电压响应度高达 2 kV/W，3 dB RF BW 至少为 50 GHz，以 315 GHz 为中心，记录 NEP 低至 3.5 pW/√Hz，在零中频和使用斩波进行验证0.5 Hz 至 2 kHz。该芯片包括焊盘在内的面积为 0.165 mm2。