This article presents a wideband balanced variable-gain low-noise amplifier (VG-LNA) implemented in a 55-nm CMOS process. The proposed LNA has two cascode stages with an interstage matching transformer to constitute a fourth-order magnetically coupled resonator with two resonant peaks. The frequency-selective gain equalization technique is proposed to compensate for the gain variation of interstage dual-resonant tanks. This VG-LNA leverages a current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP $_{\mathrm {1\,dB}}$ ) at 9 GHz from −12.2 to −5 dBm. The LNA achieves a power gain of 20.2 dB with ±0.5-dB gain variation and a noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Due to the lumped Lange couplers, the input and output matching are both better than −14 dB. This chip occupies $1.44\times0.68$ mm² area excluding pads and consumes 75 mW.

中文翻译：

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具有频率选择增益均衡技术的 6.5-12GHz 平衡可变增益低噪声放大器

本文介绍了一种采用 55 纳米 CMOS 工艺实现的宽带平衡可变增益低噪声放大器 (VG-LNA)。建议的 LNA 具有两个级间匹配变压器的共源共栅级，以构成具有两个谐振峰值的四阶磁耦合谐振器。提出了频率选择性增益均衡技术来补偿级间双谐振槽的增益变化。该 VG-LNA 利用电流控制技术实现相位不变的 18-dB 可调增益范围，测量输入 1-dB 增益压缩点 (IP $_{\mathrm {1\,dB}}$ ) 在 9 GHz 时从 −12.2 到 −5 dBm。LNA 在 6.5 至 12 GHz 范围内实现了 20.2 dB 的功率增益，增益变化为 ±0.5 dB，噪声系数 (NF) 为 3.26 dB。由于集总朗格耦合器，输入和输出匹配均优于 -14 dB。该芯片占用 $1.44\times0.68$ mm ²面积（不包括焊盘）消耗 75 mW。