This paper presents a third-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC). An FPGA development board of Altera Stratix IV was used to implement the prototype of the proposed TDC. Multirating technique is employed in this work to improve the performance over conventional TDCs. Measured results demonstrate considerable influence of multirating technique on enhancing signal-to-noise ratio (SNR), from 50.68 dB in single-rate mode to 64.8 dB in multi-rate mode (a gain of 14.12 dB). Different sampling clocks and Gated Switched-Ring Oscillators (GSROs) operating frequencies are generated utilizing built-in clock circuitries of the FPGA board. Thus, no discrete sources are needed for measurement by the proposed TDC. Moreover, the proposed design yields low complexity and power consumption since it does not consist of any calibration block and loop. Experimental results of this work and comparing them with state-of-the art Δ∑ TDCs prove that the proposed 1-1-1 MASH TDC can be incorporated in accurate and fast applications such as biosensors and ADPLLs.

本文提出了一种三阶多级噪声整形（MASH）ΔΣ时间数字转换器（TDC）。使用Altera Stratix IV的FPGA开发板来实现建议的TDC的原型。在这项工作中采用了多速率技术，以提高传统TDC的性能。测量结果表明，多速率技术对增强信噪比（SNR）有很大影响，从单速率模式下的50.68 dB提高到多速率模式下的64.8 dB（增益为14.12 dB）。利用FPGA板卡的内置时钟电路可以产生不同的采样时钟和门控开关环振荡器（GSRO）工作频率。因此，建议的TDC不需要离散源进行测量。此外，由于该设计不包含任何校准块和环路，因此提出的设计具有较低的复杂度和功耗。这项工作的实验结果并将其与最新的Δ∑ TDC进行比较，证明了所提出的1-1-1 MASH TDC可以并入准确，快速的应用中，例如生物传感器和ADPLL。