A highly energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The proposed switching scheme needs only two reference levels by using the merge-and-split technique, which eliminates the need of the extra reference voltage (V_cm). The switching procedure is performed on the simple binary weighted capacitor arrays without any capacitor-splitting. Compared with the conventional scheme, the proposed switching scheme can achieve 98.45% saving in switching energy and 75% capacitors-area reduction. Besides, because two capacitor arrays are switched symmetrically, the common-mode voltage of capacitive digital-to-analog converter (CDAC) keeps constant until the LSB cycle. The proposed switching scheme is verified in a 0.6-V 10-bit 200-kS/s SAR ADC in 40 nm CMOS technology.

提出了一种用于逐次逼近寄存器（SAR）模数转换器（ADC）的高效节能电容器切换方案。提出的开关方案通过使用合并和分离技术仅需要两个参考电平，从而消除了额外参考电压（V _cm）。切换过程在简单的二进制加权电容器阵列上执行，而无需任何电容器分裂。与传统方案相比，所提出的开关方案可以节省98.45％的开关能量，减少75％的电容器面积。此外，由于两个电容器阵列是对称开关的，因此电容性数模转换器（CDAC）的共模电压保持恒定，直到LSB周期为止。所提议的开关方案已在采用40 nm CMOS技术的0.6V 10位200kS / s SAR ADC中得到验证。