In this work the design and implementation of a High-Speed Four-Quadrant CMOS Analog multiplier is presented. The proposed multiplier uses the Gilbert cell as the main core. However, instead of processing both input and output signals in voltage or current mode, the “$x$” input signal is applied in voltage mode while the “$y$” input signal and “$o$” output signal are processed in current-mode. This approach is achieved by means of using very-low-impedance nodes at the “$y$” and “$o$” ports which also helps to enhance the overall bandwidth of the proposed multiplier. Both very-low-impedance nodes are implemented using the Flipped Voltage Follower (FVF) as high-speed high-performance low-voltage current mirror. The implemented circuit shows a bandwidth of 260 MHz for a $50\mathrm{\Omega }\Vert 30\mathrm{pF}$ load, presents a $1.5\%$ THD at 100 MHz, and consumes 7.5 mV using a $\pm 1$ V symmetric power supply. In order to validate theory and simulations, a prototype of the multiplier was fabricated and tested using a 0.5 $\mathrm{\mu }$m CMOS standard fabrication process; a silicon area consumption of 520 $\mathrm{\mu }$m × 70 $\mathrm{\mu }$m was observed. Measurements shows that the proposed multiplier is suitable for its implementation in the low corner of the Very High Frequency (VHF) band.

在这项工作中，介绍了高速四象限CMOS模拟乘法器的设计和实现。建议的乘数以吉尔伯特单元为主要核心。但是，除了以电压或电流模式处理输入和输出信号外，“$X$”输入信号在电压模式下施加，而“$ÿ$”输入信号和“$Ø$输出信号在电流模式下处理。这种方法是通过在“$ÿ$”和“$Ø$”端口，这也有助于增强建议的乘法器的整体带宽。两个低阻抗节点均使用翻转电压跟随器（FVF）来实现，作为高速高性能低压电流镜。所实现的电路显示出一个260 MHz的带宽$50\mathrm{\Omega }\Vert 30\mathrm{F}$ 加载，呈现一个 $1.5％$ 总谐波失真（THD）为100 MHz，使用 $\pm \mathrm{1个}$V对称电源。为了验证理论和仿真，制造了乘法器的原型并使用0.5进行了测试。$\mathrm{\mu }$m CMOS标准制造工艺；硅面积消耗为520$\mathrm{\mu }$米×70 $\mathrm{\mu }$观察到m。测量表明，提出的乘法器适合在甚高频（VHF）频段的低角实现。