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Synthesis of Hidden State Transitions for Sequential Logic Locking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( IF 2.7 ) Pub Date : 2021-01-01 , DOI: 10.1109/tcad.2020.2994259
Kyle Juretus , Ioannis Savidis

Oracle guided attacks, such as the satisfiability attack, are a significant concern when obfuscating an integrated circuit (IC). Partitioned finite state machine (FSM) based sequential logic locking techniques are much more resilient to oracle guided attacks due to the differences in the state space between the oracle and the IC under attack. However, susceptibility to structural attacks and the extraction of the transition state between the obfuscated and functional modes of an FSM threaten the efficacy of sequential logic locking. Therefore, a methodology to synthesize hidden state transitions (HSTs) into an FSM within an IC is developed. HSTs and logic cone modifications are utilized to further enhance the security of sequentially locked circuits by increasing the number of paths an adversary must search and reducing the susceptibility to structural attacks. An algorithm to insert hidden transitions and logic cone modifications into a netlist is developed that results in an average overhead of 6.79% in area, 7.78% in power, and 8.28% in performance across all of the ISCAS’89 sequential benchmark circuits. To modify the logic cone with two altered minterms, the average increase in area and power, beyond what is needed for the implementation of HSTs, is 26.46% and 30.30%, respectively, with no additional overhead in performance.

中文翻译:

用于顺序逻辑锁定的隐藏状态转换的综合

在混淆集成电路 (IC) 时,Oracle 引导式攻击(例如可满足性攻击)是一个重要问题。由于 oracle 和被攻击 IC 之间的状态空间不同,基于分区有限状态机 (FSM) 的顺序逻辑锁定技术对 oracle 引导的攻击更具弹性。然而,对结构攻击的敏感性以及 FSM 混淆模式和功能模式之间转换状态的提取威胁到顺序逻辑锁定的功效。因此,开发了一种将隐藏状态转换 (HST) 合成为 IC 内 FSM 的方法。HST 和逻辑锥修改用于通过增加对手必须搜索的路径数量并降低对结构性攻击的敏感性来进一步增强顺序锁定电路的安全性。开发了一种将隐藏转换和逻辑锥修改插入网表的算法,该算法可在所有 ISCAS 89 时序基准电路中实现 6.79% 的面积、7.78% 的功耗和 8.28% 的性能平均开销。用两个改变的最小项来修改逻辑锥,面积和功率的平均增加,超出了实现 HST 所需的,分别是 26.46% 和 30.30%,没有额外的性能开销。在所有 ISCAS'89 时序基准电路中,面积为 79%,功率为 7.78%,性能为 8.28%。用两个改变的最小项来修改逻辑锥,面积和功率的平均增加,超出了实现 HST 所需的,分别是 26.46% 和 30.30%,没有额外的性能开销。在所有 ISCAS'89 时序基准电路中,面积为 79%,功率为 7.78%,性能为 8.28%。用两个改变的最小项来修改逻辑锥,面积和功率的平均增加,超出了实现 HST 所需的,分别是 26.46% 和 30.30%,没有额外的性能开销。
更新日期:2021-01-01
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