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DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( IF 2.7 ) Pub Date : 2021-01-01 , DOI: 10.1109/tcad.2020.2994266
Weihua Liu , Fei Wu , Meng Zhang , Chengmo Yang , Zhonghai Lu , Jiguang Wan , Changsheng Xie

3-D NAND flash memory is gradually being widely used in solid state drives (SSDs), leading to increasing storage capacity. However, the read performance of SSD is sacrificed for decoding operations which are executed to guarantee the data reliability. No matter whether the data have bit errors, they will be sent to error correcting code (ECC) engine to decode, introducing a high read delay of SSD. Error prechecking can help to avoid the redundant decoding operations for the error-free data, but it induces extra checking overhead to the error data. Motivated by this, we carry out comprehensive experiments to analyze the distribution of bit errors in 3-D NAND flash memory. The preliminary experimental results show that there are a large number of pages read without errors in the early lifetime of 3-D NAND flash memory. Based on the observations and analyses, we propose a model to estimate the error-free ratio, and utilize it to design a dynamic error prechecking scheme (DEPS) to bypass the decoding operation for the error-free data in 3-D NAND flash memory and improve the read performance of SSD. Furthermore, by dividing a large page into small subpages, DEPS releases more error-free data, which significantly improves the read performance of SSD. Evaluation results from real-world traces demonstrate that by implementing DEPS, the average read performance of SSD is enhanced by 35%–55% with 3-D MLC NAND flash memory.

中文翻译:

DEPS:利用动态错误预检方案提高SSD的读取性能

3-D NAND 闪存正逐渐广泛应用于固态硬盘 (SSD),导致存储容量不断增加。然而,SSD 的读取性能会因执行解码操作而牺牲,以保证数据的可靠性。无论数据是否有误码,都会被送到纠错码(ECC)引擎进行解码,从而引入了SSD的高读取延迟。 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 错误预检可以帮助避免对无错误数据进行冗余解码操作,但它会给错误数据带来额外的检查开销。受此启发,我们进行了全面的实验来分析 3-D NAND 闪存中的误码分布。初步的实验结果表明,在 3-D NAND 闪存的早期生命周期中,有大量页面读取而没有错误。基于观察和分析,我们提出了一个估计无错率的模型,并利用它来设计动态错误预检方案(DEPS)来绕过对 3-D NAND 闪存中无错数据的解码操作并提高SSD的读取性能。此外,通过将大页面划分为小子页面,DEPS 释放出更多的无错数据,从而显着提高了 SSD 的读取性能。来自真实世界轨迹的评估结果表明,通过实施 DEPS,SSD 的平均读取性能与 3-D MLC NAND 闪存提高了 35%–55%。此外,通过将大页面划分为小子页面,DEPS 释放出更多的无错数据,从而显着提高了 SSD 的读取性能。来自真实世界轨迹的评估结果表明,通过实施 DEPS,SSD 的平均读取性能与 3-D MLC NAND 闪存提高了 35%–55%。此外,通过将大页面划分为小子页面,DEPS 释放出更多的无错数据,从而显着提高了 SSD 的读取性能。来自真实世界轨迹的评估结果表明,通过实施 DEPS,SSD 的平均读取性能与 3-D MLC NAND 闪存提高了 35%–55%。
更新日期:2021-01-01
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