With the increasing popularity of data-intensive applications in data centers, the switching fabric in the internode network becomes significant. Silicon-photonic switching fabrics have a bright future in data centers, which offer high bandwidth, high energy efficiency, and low latency. However, integrating a high radix multistage switching fabric in a single chip faces challenges. A large number of waveguide crossings on the silicon photonic die causes massive power loss and introduces a tremendous amount of crosstalk noise. In this article, we propose a chip partition optimization platform (POP), which can decrease the number of waveguide crossings and shorten the on-chip traversal distance of optical signals. Our algorithms can effectively reduce the power loss and crosstalk noise in silicon-photonic multistage switching fabrics, and help to improve the signal integrity. For example, compared with the common design, POP can achieve 33-dB improvement on average power loss, 42-dB improvement on the worst-case power loss, and 39-dB improvement on the worst-case signal to noise ratio, in a $1024\times1024$ butterfly based silicon-photonic switching fabric.

中文翻译：

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通过多芯片分区减少集成硅光子多级交换结构中的损耗和串扰

随着数据中心中数据密集型应用的日益普及，节点间网络中的交换结构变得重要。硅光子交换结构在数据中心具有广阔的前景，可提供高带宽、高能效和低延迟。然而，在单个芯片中集成高基数多级交换结构面临挑战。硅光子芯片上的大量波导交叉会导致大量功率损耗并引入大量串扰噪声。在本文中，我们提出了一种芯片分区优化平台（POP），它可以减少波导交叉的数量并缩短光信号的片上穿越距离。我们的算法可以有效降低硅光子多级开关结构中的功率损耗和串扰噪声，并有助于提高信号完整性。例如，与普通设计相比，POP 可以实现平均功率损耗提高 33-dB，最坏情况功率损耗提高 42-dB，最坏情况信噪比提高 39-dB，在一个$1024\times1024$蝶型硅光子交换结构。